Founding Engineer - FPGA / ASIC Engineer

At Zetta, we're building the next NVIDIA to accelerate AI discovery. Our XPU chips are state-of-the-art AI compute engines, versatile and efficient enough to support AGI, and eventually ASI, without requiring massive power infrastructure.

We're a small founding team of engineers obsessed with pushing the boundaries of compute, and we're looking for the person who will own our chip design: from FPGA prototypes today to real silicon tapeouts tomorrow.

You Are

• Scrappy. You'd rather have a design running on hardware this week than a perfect spec next quarter
• Ready to go all-in and do the work of your life
• A technical powerhouse who loves living at the hardware-software boundary
• Hungry to own a chip end-to-end: architecture, RTL, verification, bring-up
• Deeply passionate and obsessed with computing and AI
• Someone who doesn't fret when faced with near-impossible technical challenges

Your Background (important in bold)

• Background in Electrical Engineering, Computer Engineering, or you taught yourself and can prove it
• Strong digital design fundamentals (RTL, pipelining, clocking/reset strategy, latency vs. throughput tradeoffs, clean microarchitecture)
• Hands-on FPGA experience: you've taken real designs from RTL to running on a board (Xilinx/AMD or Intel/Altera), debugged timing failures at 2am, and shipped something that worked
• Synthesizable SystemVerilog/Verilog you're proud of: side projects, university work, open-source contributions, or professional experience all count
• Toolchain fluency: simulation (Verilator, VCS/Xcelium/Questa, or open-source flows), linting, synthesis, timing constraints (SDC), and iterating toward timing closure
• RTL quality instincts (assertions, CDC awareness, X-prop, code review hygiene, or the drive to build these habits fast)
• Build/flow automation (Python, Tcl, bonus points for Nix or Makefile wizardry)
• Comfort designing compute datapaths and memory subsystems: you understand bandwidth/latency-driven design even if you haven't shipped an AI accelerator yet

Huge Plus If

• Tapeout experience: university shuttle (Tiny Tapeout, MPW, Efabless), research chip, or professional. Any real silicon counts, and if you haven't taped out yet, this role is your path to it
• FPGA prototyping of large designs (partitioning, multi-FPGA, emulation-style flows)
• HW/SW bring-up experience (drivers/firmware, performance counters, profiling, debugging across the stack)
• High-speed interface/IP integration (PCIe, DDR/HBM, Ethernet, SerDes)
• Verification depth (UVM, formal, or cocotb-style Python testbenches)
• Systems programming (Linux kernel modules, low-level software)
• Autodidactic polymath with a strong mathematical background

What You'll Actually Do

• Own the FPGA prototype of our XPU architecture: get it running, keep it running, make it fast
• Write and review the RTL that becomes our first ASIC
• Drive us to tapeout by building the design flow (lint, sim, synthesis, constraints) that gets us to real silicon
• Work across architecture, verification, and physical design to hit PPA targets
• Make critical architectural decisions that will live in silicon for years

The Opportunity

• Be one of the first employees shaping a revolutionary technology
• Go from FPGA prototype to your name on a tapeout. Few roles anywhere offer that arc this early in a career
• Work directly with the founding team at our San Francisco HQ
• Grow into the technical leader of our chip team as we scale
• Highly competitive compensation + significant equity

This is THE chance to do the work of your life. The chance to put your architecture into real silicon. To go hardcore on a technical moonshot that will actually matter for over 100 to 1,000 years.

1. Introductory interview(s) (20 min)
2. In-depth technical interview (40-60 min)
3. In-person technical interview (at our SF HQ) (full day)
4. Done